SPMI Protocol Analyzer and Exerciser

SPMI Protocol Analyzer (PGY-SPMI-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between the host and design under test. SPMI (System Power Management Interface) is a MIPI (Mobile Industry Processor Interface) standard with a 2-wire synchronous serial, a bidirectional interface that connects the integrated Power Controller(PC) of a System-on-Chip (SoC) processor system with one or more Power Management Integrated Circuits (PMIC) voltage regulation systems.

PGY-SPMI-EX-PD is the leading instrument that enables the design and test engineers to test the SPMI designs for its specifications by configuring PGY-SPMI-EX-ED as master/slave, generating SPMI traffic with time variation and error injection capability and decoding SPMI Protocol packets.
 

Key features

• Supports SPMI v 1.0/ 2.0 specifications
• Ability to configure it as Master or Slave
• Supports Sole Master feature
• Supports Request Capable Slave (RCS) feature
• Supports the complex BUS arbitration process
• Generate different SPMI Packets
• Error injection such as parity error, ACK/NACK error, and Skip SSC error
• Variable SPMI data speeds (32kHz – 26Mhz1), Voltage drive levels (1.2 or 1.8), and Duty Cycle (25%,50%, and 75%).
• Simultaneously generate SPMI traffic and Protocol decode of the Bus
• Continuous streaming of protocol data to HDD/SSD
• The timing diagram of the Protocol decoded bus
• Listing view of Protocol activity
• Error Analysis in Protocol decoded data
• Ability to write exerciser script to combine multiple
• data frame generation at different data speeds
• USB2/3 host computer interface
• API support for automation in Python and C++
• Flexibility to upgrade to the unit for evolving SPMI Specification
• Optional Protocol Implementation Compliance Statement (PICS) supports scripts