I3C Protocol Analyzer and Exerciser

I3C Protocol Analyzer (PGY-I3C-EX-PD) is the Protocol Analyzer with multiple features to capture and debug communication between host and design under test. I3C Serial bus interface is emerging as a chosen interface for all future sensor connectivity in mobile phone and automotive industries. This could also be chosen as a low-cost, reliable interface for future embedded electronic applications to address the new data-intensive applications.

The PGY-I3C-EX-PD is the leading instrument that enables the design and test engineers to test the I3C designs for their specifications by configuring the PGY-I3C-EX-PD as Master/Slave to generate I3C traffic with error injection capabilities and to decode I3C protocol packets.
 

Key features

• Supports v1.0/v1.1/v1.1.1 Specifications*.
• Ability to configure it as Master and/or Slave.
• Ability to configure BCR, LVR, and DCR registers.
• Simultaneously generate I3C traffic and Protocol decode of the Bus.
• Optional Compliance Test Specifications (CTS) test script support.
• Optional support of MCTP Protocol Exerciser and Analyzer over I3C for advanced management and control protocol analysis. View application note [here].
• Supports legacy I2C slaves and masters.
• Generate different I3C SDR and HDR Packets.
• Supports IBI and Hot Plug capabilities.
• Error Injection such as CRC errors, parity errors, and ACK/NACK errors.
• Variable I3C data speeds and duty cycle.
• PMIC device support as per JEDEC DDR5 spec requirement.
• Margin test capability: Voltage and timing variation.
• Continuous streaming of protocol data between the instrument and host computer.
• Timing diagram of Protocol decoded bus.
• Listing view of Protocol activity.
• Error Analysis in Protocol Decode.
• Ability to write exerciser script to combine multiple data frame generation at different data speeds.
• USB2/3 host computer interface.
• API support for automation in Python or C++.

            *v1.1/v1.1.1 supports only one-lane commands